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Freescale Semiconductor /MK61F15WS /DDR /CR52

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Interpret as CR52

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PYWRLTBS 0RESERVED 0PHYRDLAT 0RESERVED 0RDDATAEN 0RESERVED 0RDDTENBAS 0RESERVED

Description

DDR Control Register 52

Fields

PYWRLTBS

PHY Write Latency Base
RESERVED

Reserved
PHYRDLAT

PHY Read Latency
RESERVED

Reserved
RDDATAEN

Read Data Enable
RESERVED

Reserved
RDDTENBAS

Read Data Enable Base
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data